Typically, large arrays of field-effect transistors ("FETs") fabricated on a single semiconductor chip are employed as read-only memories ("ROMs") for the storage of digital data. In general, metal-oxide FETS ("MOSFETs") have been the FET of choice for such ROMs because of the superior impedance characteristics which they exhibit. One well-known structure for achieving high storage density within a FET ROM requires the individual FETs to be fabricated so that they are connected in series. While this effectively reduces the area occupied by the FETs, it requires the use of an elaborate scheme to access and read the contents of the memory. Furthermore, the time required to access and read this type of series FET ROM is typically proportional to the square of the number of individual FETs connected in series. Obviously this results increasingly greater delays as memory size is increased.
An alternative to the serial FET ROM architecture is a parallel arrangement comprised of multiple groupings of FETs. The FETs within each grouping are connected in a parallel to a single output called a bit line. The time required to access and read such ROMs is proportional to the number of FETs connected in parallel to each bit line. While this parallel architecture provides an improvement in access and read time over the serial architecture, it poses a problem with respect to maximizing the number of memory sites (i.e., individual transistors) which can be fabricated on a semiconductor chip of any given size.
Ideally, it would be desirable to have a fabricated device (in this case, an individual FET) fit within the minimum period lattice structure of the particular semiconductor chip being produced. The minimum size of a feature that can be reliably fabricated upon a semiconductor chip is a function of the particular materials and processing techniques employed to produce that chip. Regardless of what the minimum feature size is, the minimum period of any regular square lattice structure that can be fabricated on a semiconductor chip is equal to approximately three times this minimum feature size. In other words, the most compact lattice structure that could be fabricated would consist of lines one minimum feature size wide, separated from each other by a distance equal to one minimum feature size. If one bit of information were stored at every intersection of this compact lattice, the highest possible data storage density for that particular technology would be achieved.
Unfortunately, a conventional parallel FET ROM architecture cannot be fabricated to conform with a minimum lattice structure. This is due to a design peculiarity of typical FETs which requires current to flow between the FET source and drain regions in a direction parallel to the surface of the semiconductor material that composes the FET. The parallel current flow is dictated by the placement of the FET source and drain, which are diffused or implanted into the surface of a semiconductor material. The semiconductor material between the source and drain provides a conductive channel, parallel to its surface, which serves as a gate for the FET.